Careers

Distributed Storage Software Engineer

Responsibility:

  • Design, build, and benchmark distributed storage systems (e.g., Ceph and HDFS). Optimize distributed storage software stack on Innogrit hardware. 

Requirement:

  • MS or above in Computer Science/Engineering or equivalent;
  • Experience in building scalable, high-performance, highly available distributed systems;
  • Experience in working with big data technologies such as Spark, Hadoop ecosystems, Kafka, Zookeeper, Elasticsearch, Yarn, MapReduce, Storm, HBase and Cassandra;
  • Familiar with Linux operating system and its files system;
  • Familiar with Hadoop ecosystems and distributed file systems (HDFS, GFS, …);
  • Familiar with SQL and NoSQL database.

Hardware Engineer

Responsibility: 

  • Layout, PCB design, system bringup and debugging in the lab. 

Requirement:

  • MS in Electrical Engineering;
  • 5+ years in designing boards and FPGA with Verilog;
  • Experience with Orcad/Allegro and layout supervision;
  • Good understanding of signal integrity and layout simulation tools like Hyperlynx or PowerSI;
  • System bringup and debug in lab. Usage of Oscilloscopes, Logic Analyzers and debug tools like Realview, Chipscope;
  • Self-driven and motivated to work in an active environment.

Machine Learning Architect

Responsibility: 

  • Optimize hardware for machine learning kernels and evaluate performance and power efficiency.

Requirement:

  • MS in Electrical Engineering;
  • 3+ years of machine learning experience;
  • Strong understanding of state-of-the-art techniques such as deep neural networks;
  • Strong background in hardware architecture (pipelining, memory hierarchies, DRAM,power and area estimates) and mathematical;
  • Strong software skills in C++; Ability to deeply understand application needs and algorithms.

Additional Success Factors:

  • Experience with ARM or POWER ISA;
  • Ability to proactively take on responsibilities and competent to work in a start-up environment;
  • Ability to work with cross-functional teams.

Digital Design Lead

Responsibility: 

  • Cover all aspects of digital SoC design, focusing on architecture, RTL, verification, logic synthesis, and timing analysis to deliver a design meeting power, performance and area goals.

Requirement:

  • BS and/or MS in Electrical Engineering;
  • 12+ years of RTL design/architecture experience;
  • Proven record with the definition and development of complex SoCs;
  • Know both frontend and backend flows;
  • Strong knowledge of Verilog, System Verilog, Synthesis and Static Timing Analysis;
  • Self-motivated and able to work effectively both independently and in a team.

Additional Success Factors:

  • Experience with designing for ARM CPU based SoC;
  • Ability to proactively take on responsibilities and competent to work in a start-up environment;
  • Management experience.

Verification Engineer

Responsibility: 

  • Create leading edge constrained-random verification environments and drive functional correctness of SoCs.

Requirement:

  • BS and/or MS in Computer Science;
  • 5+ years of experience in ASIC/SoC verification with SV/UVM environments;
  • In-depth knowledge of verification flows,constrained random verification process, functional coverage, code coverage, assertion methodology & philosophy;
  • Team player with excellent communication skills and the desire to take on diverse challenges.
  • Additional Success Factors:
  • Advanced knowledge of CPU & SoC architecture/design;
  • Experience in verifying data storage protocols such as SATA, PCIe, NVMe;
  • Knowledge of formal verification, hardware emulation.

Senior Design Engineer

Responsibility: 

  • Cover PCIe and other IP block designs, focusing on architecture, RTL, logic synthesis, and timing analysis to deliver design target goals.

Requirement:

  • BS/MS in Electrical Engineering;
  • 12+ years of RTL design and/or architecture experience;
  • Expertise in PCIe standards including SR-IOV designs and PCIe Transaction Layer;
  • Experience in PCIe application layer implementation,PCI logic analyzers, PCIe components;
  • Know Verilog, System Verilog, Synthesis and Static Timing Analysis.

Additional Success Factors:

  • Ability to proactively take on responsibilities and competent to work in a start-up environment.

Senior ECC Engineer

Responsibility: 

  • Cover error correction code designs and deliver design meeting target power, performance and area goals.

Requirement:

  • BS/MS in Electrical Engineering;
  • 12+ years of ECC design and/or architecture experience;
  • Expertise in BCH, LDPC, and proven track record;
  • Knowledge of logic design principles along with timing and power implications;
  • Strong knowledge of Verilog, System Verilog, Synthesis and Static Timing Analysis.

Additional Success Factors:

  • Ability to proactively take on responsibilities and competent to work in a start-up environment.

Analog Design Lead

Responsibility: 

  • Provide analog and mixed-signal circuits. Lead analog/mixed-signal design team to deliver designs goals.

Requirement:

  • BS/MS in Electrical Engineering;
  • 10+ years of analog circuit design experience;
  • Experienced with both high and low speed interfaces like GPIOs, PCIe, NVMe, SAS, etc;
  • Proven track record of successful analog circuitry delivery for SoC integration;
  • Self-motivated and able to work effectively both independently and in a team.

Additional Success Factors:

  • Ability to proactively take on responsibilities and competent to work in a start-up environment;
  • Management experience.

Backend P&R Design Lead

Responsibility: 

  • Generate high quality deliverables to backend vendor. Establish milestones and goals to ensure schedule and quality.

Requirement:

  • BS/MS in Electrical Engineering;
  • Solid chip development experience;
  • 10+ years of experience in place & route and physical design, including floor planning, static timing verification and layout verification;
  • Prior experience supervising team members and contractors;
  • Self-motivated and able to work effectively both independently and in a team.

Additional Success Factors:

  • Ability to proactively take on responsibilities and competent to work in a start-up environment.

Senior RTL Engineer/Architect, Hardware Accelerators

Responsibility: 

  • Identify & define hardware accelerators along with all SoC design, deliver a design meeting target power, performance and area goals.

Requirement:

  • BS/MS in Electrical Engineering;
  • 10+ years of RTL design and/or architecture experience;
  • Strong understanding of Compression (DEFLATE, LZS, Huffman Encoding, Dedup, etc.) or Crypto algorithms (symmetric & asymmetric key algorithms) or SSL/TLS protocol;
  • Strong knowledge of Verilog, System Verilog, Synthesis and Static Timing Analysis;
  • Self-motivated and able to work effectively both independently and in a team.

Linux Driver Engineer

Responsibility: 

  • Design and implement drivers and libraries that communicate with our chip.

Requirement:

  • BS/MS in Computer Science;
  • 5+ years experience writing device drivers for Linux;
  • Experience with networking or storage stacks;
  • Architectural sense;
  • Ability to write correct C or C++ code fast;
  • Experience with operating system bypass and zero-copy techniques, including RDMA;
  • Experience with PCIe Express single-root IO virtualization (SR-IOV).

Firmware Engineer

Responsibility: 

  • Design and implement the infrastructure software.

Requirement:

  • BS/MS in Computer Science;
  • 5+ years experience in firmware development;
  • Experience with embedded CPU (preferably ARM) and RTOS;
  • Experience in code generation;
  • Experience with regression and product-level testing;
  • Ability to write correct C or C++ code fast;
  • Experience in Python and its various libraries and tools;
  • Self motivated, independent and proactive.

Additional Success Factors:

  • Great communication and organizational skill to communicate with other developers about their requirements and keep track of them.

For any job inquiries or resume, please email jobs@innogritcorp.com